Verification of Hardware combining Multiplication, Division Square Root. / Walter, Colin D.

In: Microprocessors and Microsystems, Vol. 19, 1995, p. 243-245.

Research output: Contribution to journalArticle

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Verification of Hardware combining Multiplication, Division Square Root. / Walter, Colin D.

In: Microprocessors and Microsystems, Vol. 19, 1995, p. 243-245.

Research output: Contribution to journalArticle

Harvard

APA

Vancouver

Walter CD. Verification of Hardware combining Multiplication, Division Square Root. Microprocessors and Microsystems. 1995;19:243-245.

Author

Walter, Colin D. / Verification of Hardware combining Multiplication, Division Square Root. In: Microprocessors and Microsystems. 1995 ; Vol. 19. pp. 243-245.

BibTeX

@article{e7fff85c84fb47139033264a8ea2b562,
title = "Verification of Hardware combining Multiplication, Division Square Root",
author = "Walter, {Colin D.}",
year = "1995",
language = "Undefined/Unknown",
volume = "19",
pages = "243--245",
journal = "Microprocessors and Microsystems",
issn = "0141-9331",
publisher = "Elsevier",

}

RIS

TY - JOUR

T1 - Verification of Hardware combining Multiplication, Division Square Root

AU - Walter, Colin D.

PY - 1995

Y1 - 1995

M3 - Article

VL - 19

SP - 243

EP - 245

JO - Microprocessors and Microsystems

JF - Microprocessors and Microsystems

SN - 0141-9331

ER -