Improvements to instruction identification for custom instruction set design

High performance embedded systems are required to satisfy tight power, unit cost, and performance criteria. An embedded system will only run one application in its lifetime, so in principle there are opportunities to ‘tune’ the embedded system to the target applica- tion. In today’s highly competitive marketplace such tuning must be achievable without large-scale manual intervention.
An obvious way of tuning embedded processor architectures is to remove unused registers and instructions thus saving hardware real estate. More interestingly, common sequences of instructions could be implemented as special custom instructions. Such instructions have the potential to reduce code size and instruction fetch time along with overall execution time.
This thesis describes new algorithms for the generation of can- didate custom instructions; providing an analysis of weaknesses in current approaches and giving experimental evidence and proofs of correctness and time complexity.