Improved Linear Systolic Array for Fast Modular Exponentiation. / Walter, Colin D.

In: IEE Proc. Computers and Digital Techniques, Vol. 147, No. 5, 01.09.2000, p. 323-328.

Research output: Contribution to journalArticle

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Improved Linear Systolic Array for Fast Modular Exponentiation. / Walter, Colin D.

In: IEE Proc. Computers and Digital Techniques, Vol. 147, No. 5, 01.09.2000, p. 323-328.

Research output: Contribution to journalArticle

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APA

Vancouver

Walter CD. Improved Linear Systolic Array for Fast Modular Exponentiation. IEE Proc. Computers and Digital Techniques. 2000 Sep 1;147(5):323-328.

Author

Walter, Colin D. / Improved Linear Systolic Array for Fast Modular Exponentiation. In: IEE Proc. Computers and Digital Techniques. 2000 ; Vol. 147, No. 5. pp. 323-328.

BibTeX

@article{a1fc45ce13d34876b8a8038838f8aba4,
title = "Improved Linear Systolic Array for Fast Modular Exponentiation",
author = "Walter, {Colin D.}",
year = "2000",
month = sep,
day = "1",
language = "Undefined/Unknown",
volume = "147",
pages = "323--328",
journal = "IEE Proc. Computers and Digital Techniques",
number = "5",

}

RIS

TY - JOUR

T1 - Improved Linear Systolic Array for Fast Modular Exponentiation

AU - Walter, Colin D.

PY - 2000/9/1

Y1 - 2000/9/1

M3 - Article

VL - 147

SP - 323

EP - 328

JO - IEE Proc. Computers and Digital Techniques

JF - IEE Proc. Computers and Digital Techniques

IS - 5

ER -