Characterising a CPU Fault Attack Model via Run-Time Data Analysis. / Kelly, Martin; Mayes, Keith; Walker, John F.

2017. Paper presented at IEEE International Symposium on Hardware Oriented Security and Trust (HOST), McLean, VA, United States.

Research output: Contribution to conferencePaper



  • PID4658763

    Accepted author manuscript, 995 KB, PDF-document

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Abstract—Effective software defences against errors created by
fault attacks need to anticipate the probable error response of the
target micro-controller. The range of errors and their probability
of occurrence is referred to as the Fault Model. Software defences
are necessarily a compromise between the impact of an error, its
likelihood of occurrence, and the cost of the defence in terms
of code size and execution time. In this work we first create a
fault insertion system and then use it to demonstrate a technique
for precisely triggering and capturing individual error responses
within a running micro-controller. This enables a more realistic
calibration of a micro-controller’s fault model. We apply the
system to a representative micro-controller and the results show
that error insertion is far more predictable than anticipated, and
is consistent over a wide range of experimental tolerances. This
observation undermines some widely deployed software defences
recommended for fault attack protection.
Original languageEnglish
Number of pages6
StatePublished - 19 Jun 2017
EventIEEE International Symposium on Hardware Oriented Security and Trust (HOST) - The Ritz-Carlto, McLean, VA, United States
Duration: 1 May 20174 May 2017


ConferenceIEEE International Symposium on Hardware Oriented Security and Trust (HOST)
Abbreviated titleHOST
CountryUnited States
CityMcLean, VA
Internet address
This open access research output is licenced under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported License.

ID: 27773426