HLS design of a reconfigurable Quaternion Neural Network hardware accelerator

In this paper, a rapid field-programmable gate array (FPGA) prototyping of a general quaternion based Artificial Neural Network (qANN) algorithm is investigated. The design method involves the description of the qANN behaviour in C programming language and its hardware implementation, using VITIS High-Level Synthesis (HLS) tool. Simulations and FPGA implementation results and their analysis are presented in terms of performance (data accuracy) vs hardware resources used, and data throughput. The design method proves to be an attractive alternative to hardware description languages based design, opening the field of FPGA acceleration of complex algorithms to a larger audience.