Efficient quaternion multiplication/division models as building blocks of quaternion based algorithms implemented in FPGA

Quaternion multiplication/division are essential arithmetic operations found in the majority of quaternion based algorithms. Their usage has been widely reported in literature, demonstrating their importance. However, there are no reports that show a systematic approach in designing a hardware implemented quaternion multiplier/divider and assess their implementation performances. The work reported in this paper addresses this gap and presents a series of quaternion multiplication/division algorithms, proposes corresponded design models and analysis their hardware implementation performances in terms of throughput (latency, iteration interval and minimum clock period) and hardware resources used. The best performant models are highlighted versus data quantisation, speed and resources and offered as building blocks for efficiently implementing more complex quaternion based algorithms.