Abstract
A bit-serial modular multiplier is presented which uses a table look-up method to perform modular reduction. Since the clock frequency is independent of word length, this design is most useful when dealing with large integers, and is required by many modern cryptographic system
| Original language | Undefined/Unknown |
|---|---|
| Pages (from-to) | 1664 |
| Number of pages | 1 |
| Journal | Electronics Letters |
| Volume | 25 |
| Issue number | 24 |
| Publication status | Published - 1 Nov 1989 |