Acceleration of Timing-Aware Gate-Level Logic Simulation Through One-Pass GPU Parallelism

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Original language	English
Pages (from-to)	1-12
Number of pages	12
Journal	IEEE Transactions on Computers
Early online date	13 May 2025
DOIs	https://doi.org/10.1109/TC.2025.3569135
Publication status	E-pub ahead of print - 13 May 2025

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title = "Acceleration of Timing-Aware Gate-Level Logic Simulation Through One-Pass GPU Parallelism",

author = "Weijie Fang and Yanggeng Fu and Jiaquan Gao and Longkun Guo and Gregory Gutin and Xiaoyan Zhang",

year = "2025",

month = may,

day = "13",

doi = "10.1109/TC.2025.3569135",

language = "English",

pages = "1--12",

journal = "IEEE Transactions on Computers",

issn = "0018-9340",

publisher = "IEEE Computer Society",

}

TY - JOUR

T1 - Acceleration of Timing-Aware Gate-Level Logic Simulation Through One-Pass GPU Parallelism

AU - Fang, Weijie

AU - Fu, Yanggeng

AU - Gao, Jiaquan

AU - Guo, Longkun

AU - Gutin, Gregory

AU - Zhang, Xiaoyan

PY - 2025/5/13

Y1 - 2025/5/13

U2 - 10.1109/TC.2025.3569135

DO - 10.1109/TC.2025.3569135

M3 - Article

SN - 0018-9340

SP - 1

EP - 12

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

ER -